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[SCM] Source

Description: PWM Verilog源代码，可以通过仿真测试-PWM Verilog source code, can be tested through simulation
Platform: | Size: 2048 | Author: shuichengwen | Hits:

[VHDL-FPGA-Verilog] an501_design_example

Description: PWM文件 用于CPLD，学习如何用VHDL语言写程序-PWM files for CPLD, learn how to write VHDL language program
Platform: | Size: 285696 | Author: xiaox | Hits:

[Software Engineering] cpldpwm

Description: cpld的PWM输出控制，初学cpld良好例程-CPLD output of PWM control, a good beginner routine CPLD
Platform: | Size: 60416 | Author: 做人要厚道 | Hits:

[SCM] ctr_rev_160us

Description: pwm控制模块 使用过很多次-pwm control module to use many times
Platform: | Size: 2009088 | Author: 黄坚 | Hits:

[VHDL-FPGA-Verilog] PWM_control_motor

Description: This a project about PWM. Application in motor speed control-This is a project about PWM. Application in motor speed control
Platform: | Size: 737280 | Author: nguyen hung | Hits:

[VHDL-FPGA-Verilog] pwm_source

Description: Altera官网上关于SOPC中自定义组件（PWM）的实例，官网上现在没了。。可很多书上都在用-Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . .
Platform: | Size: 10240 | Author: lion | Hits:

[VHDL-FPGA-Verilog] Avalon_PWM_IP_pwm

Description: Avalon总线下的PWM的IP模块。基于VHDL语言。-Avalon Bus IP of the PWM module. Based on the VHDL language.
Platform: | Size: 20480 | Author: 李超 | Hits:

[VHDL-FPGA-Verilog] EP1C3_12_1_2_MOTO

Description: 基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写，压缩包里是Quartus下的工程。-FPGA-based PWM DC motor control and stepper motor-driven control of a breakdown. The use of VHDL language, compression bag is under the Quartus project.
Platform: | Size: 1193984 | Author: deadtomb | Hits:

[Industry research] pwm

Description: counter for pwm in order to generate pulses for the module it is required to write a program for counter
Platform: | Size: 2048 | Author: penguin | Hits:

[VHDL-FPGA-Verilog] pmw2ppm

Description: Vhdl code PPM to pwm converte
Platform: | Size: 4096 | Author: SANTOSH | Hits:

[VHDL-FPGA-Verilog] pwm_gen

Description: PWM _Generator VHDL code
Platform: | Size: 1024 | Author: kiran | Hits:

[VHDL-FPGA-Verilog] pwmtest

Description: 拨码开关控制PWM的占空比为16级，分别对应电压3.3伏16分之一的倍数-DIP switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
Platform: | Size: 175104 | Author: panda | Hits:

[VHDL-FPGA-Verilog] PWMtest

Description: PWM 转模拟信号 拨码开关控制 PWM 的占空比为16级，分别对应电压3.3伏16分之一的倍数-DIP switch to an analog signal PWM switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
Platform: | Size: 140288 | Author: panda | Hits:

[Embeded-SCM Develop] 1

Description: Avalon总线的pwm定制，在niosII下定制了PWM通过avalon总线链接到niosII上，绝非一般的实验，应用在实际的工控项目中。-Avalon bus pwm custom, under the custom of the PWM in the niosII by avalon bus link to niosII on the experiment in general not applied in real industrial control projects.
Platform: | Size: 584704 | Author: 陈泸华 | Hits:

[VHDL-FPGA-Verilog] FPGAPWM

Description: 使用VHDL设计基于CPLD_FPGA逆变电源的PWM波形-Using the VHDL design is based on the PWM inverter waveform CPLD_FPGA
Platform: | Size: 41984 | Author: 田龙敬 | Hits:

[VHDL-FPGA-Verilog] fpga-pwm

Description: 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and simulation results, this procedure can be embedded directly used to do routines.
Platform: | Size: 1163264 | Author: 黄家武 | Hits:

[MultiLanguage] final

Description: nice control program pwm
Platform: | Size: 892928 | Author: adhominen | Hits:

[VHDL-FPGA-Verilog] VGAPWM

Description: FPGA PWM control and VGA display use VHDL language with simulation.
Platform: | Size: 309248 | Author: xiaominjin | Hits:

[Driver Develop] FPGA_SOPC_PWM

Description: 将此文件解压缩，会得到一个"ip"目录，将此目录放入你的项目中，就可以在sopc中import到一个叫pwm的组建了。解压缩还会得到一个C语言文件，它是与硬件配合的Nios2_C代码 -Extract this file will get an " ip" directory into this directory in your project, you can import into the sopc in the formation of a called pwm. Extract will get a C language file, which is the code and hardware co-ordination Nios2_C
Platform: | Size: 5120 | Author: 于艳超 | Hits:

[VHDL-FPGA-Verilog] pwm

Description: vhdl model for a 3 phase system
Platform: | Size: 2048 | Author: dante | Hits:
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